1. Field of the Invention
The present invention relates to a programmable logic block, and more particularly to a programmable logic block suitable for designing an asynchronous circuit.
2. Description of Related Art
Recently, due to a huge demand for electronic chips and time taken to meet the market requirement, the field programmable grate array (FPGA) has become an optimum choice for circuit design. The architecture of the FPGA is primarily categorized into the SRAM-base model and the anti-fuse model in the design. The SRAM-base is featured by rewritability, low power consumption and in-circuit configurability, but it requires download of data from the external device and an external power source to maintain data. Thus, the SRAM-base is adapted to a multiple-writing circuit design. On the other hand, the anti-fuse has a one-time programmable (OTP) feature to provide better protection for security, but it is unable to be further modified. Thus, the anti-fuse is adapted to a write-once circuit design. Nevertheless, the industry currently does not provide any FPGA system designed specifically for the asynchronous protocol because the asynchronous circuit is complex and not easy to design. The industry does not have either a comprehensive set of design flows or appropriate software for the use of engineers. As such, an asynchronous circuit system design using the FPGA system will involve a number of useless circuits, causing waste of chip area and inefficiency. Therefore, the aforementioned FPGA system has some defects in the process of asynchronous circuit design, and thus needs to be improved.